Hybrid Substrates for Chiplet Design and Heterogeneous Integration Packaging

The fan-out panel-level chip-last method for chiplet design and heterogeneous integration packaging is presented. Emphasis is placed on the design, materials, process, and fabrication of: (a) heterogeneous integration of chips with $50\mu$m pitch (minimum); (b) fine metal linewidth (L), spacing (S) and thickness (H) redistribution-layer (RDL)-substrates, (c) hybrid substrates, and (d) chips to hybrid substrate bonding and underfilling. Reliability assessments by simulation and test are performed.