Design and Implementation of Reconfigurable RS Processor

As a representative error correction code, Reed-Solomon code is widely used in the related fields of information transmission and storage for its excellent performance. Application Specific Integrated Circuit (ASIC) is a mainstream hardware implementation solution. Although it has a high energy efficiency ratio, it has poor flexibility and cannot be applied to other communication environments. It needs to be redesigned and tape-out according to the application requirements, and the cost is enormous. Given the above problems, this paper proposes a coarse-grained reconfigurable processor suitable for RS encoding and decoding technology, which can meet the requirements of Forward Error Correction (FEC) technology in different communication scenarios. The design can conFigure RS codec circuits with different codes, different code lengths and different degrees of parallelism according to the instructions, and can support dynamic configuration of the processor under the condition that the total code length is constant and the signal code length is adjustable. There are broad application prospects in terms of flexibility.