A Stable Low Leakage Power SRAM with Built-In Read/Write-Assist Scheme using GNRFETs for IoT Applications

Design of circuits using graphene nanoribbon field-effect transistors (GNRFETs), as promising next-generation devices, can improve total performance of a chip due to offering excellent properties. However, GNRFETs are in the early stage of design, and the studies of process-voltage-temperature (PVT) variations on their performance are very crucial. Therefore, this paper aims to design, simulate, and evaluate a novel stable fully differential 12 T (SFD12T) SRAM using GNRFETs under PVT variations. Simulation results in 16 nm GNRFET technology at 0.5 V show that the proposed design improves read stability/writability by 2.11x/1.09 x compared to fully differential 8 T (FD8T: as a basic cell) due to using built-in read/write-assist scheme, which forces "0" storing node to ground during a read operation and cuts pull-down path off during a write operation, respectively. An improvement of at least 4.79% (18.55% compared to FD8T) in leakage power is achieved due to stacking of transistors. The fourth-best read/write energy among eight studied SRAMs is related to the proposed design. In addition, it can support the bit-interleaving architecture because it eliminates half-select disturbance issues. Generally, the proposed design is the best SRAM from the figure of merit (FOM) point of view, so it can be an optimal choice for Internet-of-Things applications.