First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications

S-W Chang, T-H Lu,C-Y Yang,C-J Yeh,M-K Huang, C-F Meng,P-J Chen,T-H Chang, Y-S Chang, J-W Jhu,T-Z Hong,C-C Ke,X-R Yu,W-H Lu,M. A. Baig,T-C Cho,P-J Sung,C-J Su,F-K Hsueh,B-Y Chen, H-H Hu,C-T Wu,K-L Lin,W. C-Y Ma,D-D Lu,K-H Kao,Y-J Lee,C-L Lin,K-P Huang,K-M Chen,Y. Li,S. Samukawa,T-S Chao,G-W Huang,W-F Wu,W-H Lee,J-Y Li,J-M Shieh,J-H Tarng,Y-H Wang,W-K Yeh

2021 IEEE International Electron Devices Meeting (IEDM)（2021）

Cited 33|Views20

Key words

first demonstration,dual workfunction gate,dual-workfunction gate complementary FET inverters,n-type IGZO,p-type polysilicon channels,dual-workfunction gate structure,adjusted gate biasing,channel potential,high-frequency IGZO RF devices,p-type silicon isolation,etching process,fluorine-based gas,high-etching selectivity,IGZO surface,low leakage current shallow passivation layer

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