Hierarchical simulation of nanosheet field effect transistor: NESS flow

Nanosheet gate-all-around transistor devices have been an important contenders for future technology nodes. Compared to FinFETs they have superior electrostatic control. The nanosheet architecture can also be vertically stacked thus achieving higher drive current on a same footprint area compared to a single nanowire or nanosheet. Accurate device simulations are crucial for the development and the optimization of the nanosheet transistors. With this in mind, we have developed and report a hierarchical simulations flow implemented in the Glasgow Nano-Electronic Simulation Software (NESS) in order to enable the accurate simulation and optimization of the nanosheet transistors. In this work we have carried out device simulations and showed that the more accurate NEGF simulations can be used for the calibration of the classical DD simulations within one single toolbox. Additionally we showed that the EME module can be used to extract the effective masses for confined structure like the nanosheet.