Design of a Feature Extracted CMOS Image Sensor with a Novel Integrator and a Configurable ADC

Design of a feature extracted CMOS image sensor (CIS) with a new integrator and configurable analog-to-digital converter (ADC) is described. Since a feature extraction is normally executed at the digital block of image signal processor (ISP), an ISP must be connected to the end of CIS. Namely, the system of feature extraction has been normally based on two-chip solution with CIS and ISP. In case of simple feature extraction, however, the block of ISP can be eliminated, if a special working block could be inserted in the middle of CIS. In order to implement a feature extracted CIS, a new integrator to detect the codes of neighboring pixels is proposed. Further, a configurable 8-bit and 1-bit single-slope ADC is discussed. To verify the performance, a prototype of CIS has been fabricated with an 180nm CMOS technology. The number of pixel array is 1920 x 1380, and the frame rate is 60. The measured power consumption is only 9mW, and it is drastically reduced compared to other conventional ones.