An 8-ENOB Sampling-Rate Reconfigurable Asynchronous SAR ADC for Space Applications

This paper presents a novel architecture and design of an 8-bits Asynchronous Successive-Approximation-Register (ASAR) Analog-to-Digital-Converter (ADC) targeted for multi-channel readout ASICs for space applications. Unlike other ASAR ADCs, this ADC uses a variable delay cell which provides the desired delay only to the rising-edge of the internally generated clock signal. In addition, the ADC has the capability to conFigure its sampling-rate (f s ), from typical 40 kS/s to 167 kS/s, with proportional power consumption. Moreover, the proposed architecture is adaptable to the frequency and duty cycle of the only external low duty cycle ‘CLKsampling’ signal, which can be customized for the desired application. Designed in a 0.35 $\mu$m CMOS process with a supply voltage of 3.3 V, the ADC achieves in schematic-level simulations an ENOB of 7.93 bits, a peak SNDR of 49.5 dB, DNL and INL of <0.1 LSB at typical f s of 40 kS/s. The ADC achieves the best FoM of 622 fJ/C-step at its maximum f s , where it has the same ENOB and SNDR as at typical f s . With the digital section and delay cell at 1.2 V including level-shifters, the ADC FoM improves to 211 fJ/C-step at maximum f s without performance degradation.