VLSI Implementation of RISC MCU with In-Circuit Debugger

A VLSI architecture of the NTOU_LF1826 MCU with an ICD (In-Circuit Debugger) is proposed in this study. We use Verilog HDL (Hardware Description Language) to construct the Soft IP of the NTOU_LF1826 RISC MCU with ICD architecture and go through emulation verification under ModelSim environment. Altera DE10 board and ICD software platform are used to verify the FPGA results. Furthermore, by using the Cell-Based design flow and Taiwan Semiconductor Research Institute (TSRI) EDA cloud platform, VLSI implementation of the RISC MCU under the TSMC 0.18 µm CMOS technology reveal that the size is 1190 × 1190 μm and clock rate is 100 MHz. The two main parts of the NTOU_LF1826 MCU with ICD, the hardware and software are presented in this study. For software, we develop an ICD in-circuit debugger that allows users to observe internal registers immediately. In terms of hardware, we provide two modes, Debug and Run. Under Run mode, the MCU processes as usual, while under Debug mode, the in-circuit debugger has functions such as Reset, Step Into, Step Over, Read Register, and Write Register, five main functions. Communication of software and hardware is conducted by using the SPI (Serial Peripheral Interface) protocol. NTOU_LF1826 MCU has Run mode as default to properly execute programs. Therefore, the proposed NTOU_LF1826 RISC MCU VLSI architecture and integrated development environment enable users to easily use the RISC MCU.