A 0.6 ㎛ Small Pixel for High Resolution CMOS Image Sensor with Full Well Capacity of 10, 000e- by Dual Vertical Transfer Gate Technology.

In this paper, we developed a 0.6 ㎛ pixel with full well capacity (FWC) of 10,000e-using dual vertical transfer gate (D-VTG) technology. FWC of D-VTG increased by 60% compared to single vertical transfer gate (S-VTG). The D-VTG improved the transfer capability compared to S-VTG by increasing the controllability of TG voltage. We also optimized electron transfer by the gap, depth, and taper slope of VTGs. Through the D-VTG technology, we successfully demonstrated a prototype 200Mp CMOS image sensor (CIS) with 0.6 ㎛ pixels.