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First Demonstration of 1-bit Erase in Vertical NAND Flash Memory.

Symposium on VLSI Technology (VLSI Technology)(2022)

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Abstract
We propose for the first time a method for erasing one selected cell in Vertical NAND (VNAND) flash memory. By controlling the voltage applied to the terminals (switch devices and cells) of the VNAND string array, 1-bit erase (GIDL generation) of one selected cell and erase inhibition (GIDL suppression) of unselected cells are successfully verified. Compared to the existing method, the 1-bit erase method reduces the current fluctuation by 17 times at an I BL of 50 nA and reduces the V th dispersion of >2 V to ~0.2 V or less.
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Key words
VNAND,1-bit erase,GIDL,IBL (or Vth) dispersion
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