Intel 4 CMOS Technology Featuring Advanced FinFET Transistors Optimized for High Density and High-Performance Computing

B. Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang,D. Basu, S. Bendapudi,D. Bergstrom, R. Bhandavat, S. Bhowmick,M. Buehler, D. Caselli, S. Cekli, Vrsk. Chaganti, Y. J. Chang,K. Chikkadi,T. Chu, T. Crimmins, G. Darby,C. Ege, P. Elfick, T. Elko-Hansen,S. Fang, C. Gaddam,M. Ghoneim,H. Gomez,S. Govindaraju, Z. Guo,Walid M. Hafez,M. Haran,M. Hattendorf, S. Hu,A. Jain,S. Jaloviar,M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy,S. Klopcic, D. Krishnan,J. Leib, Y.-T. Lin,N. Lindert,G. Liu, O. Loh,Y. Luo, S. Mani, M. Mleczko, S. Mocherla,P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar,L. Pipes,P. Plekhanov,Chetan Prasad,M. Prince, G. Ramalingam,R. Ramaswamy, J. Riley, J. R. Sanchez Perez,J. Sandford,A. Sathe, F. Shah, H. Shim,S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta,T. Troeger,X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu,P. Yashar, J. Yaung, K. Yoon, N. Young

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

Cited 22|Views24

Key words

enhanced copper metallurgy,line resistance,improved electromigration,process flow,EUV lithography,4PVT,4NVT,high-performance library,Intel 7,high performance logic library,Moores law,advanced CMOS FinFET technology,high-performance computing,Intel 4 CMOS technology,interconnect stack,speed requirements,voltage 190.0 mV,voltage 180.0 mV

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