A Hardware Optimized High Throughput LDPC Decoder Supporting 3 Tb/s in 28 nm CMOS

This paper proposes an optimized pipelined decoding architecture with seven processing stages for unrolled LDPC decoders. Pipelined design with seven register layers significantly increases the resulting clock frequency. Moreover, we investigate the optimal layout shape for unrolled decoders. This paper's fastest decoder is based on the IEEE 802.11n LDPC(1944,1620) parity-check matrix and achieves 2937 Gb/s of coded throughput after physical design. By optimizing the pipeline, floorplan, and employing a codeword length of 1944 bits, we increased the throughput by 241% compared to the previous fastest LDPC decoder presented in the literature. To the best of our knowledge, it is the fastest soft-decision decoder published so far. The standard min-sum approach is employed for decoding, and the proposed improvements consider changes only on the hardware level.