High-Level Early Power Estimation of FPGA IP Based on Machine Learning

When high speed and high performance are key features of a specific FPGA-based system, increase in energy consumption becomes the main hurdle to be tackled while keeping a trade-off between speed, performance and power consumption. Therefore, power optimization has become a major concern for most digital hardware designers, particularly in early design phases and especially in limited power budget systems (battery-operated hand-held devices, electro-optical pluggable modules, IoT and green energy systems, etc.). In this paper we present and evaluate an accurate power modeling and estimation technique based on machine learning. We estimate the power consumption of specific digital circuits based on control and input signals characteristics. The proposed Artificial Neural Network (ANN) model is trained using real measurement data sets appended to the input switching activity information. Upon applying the proposed model to an FPGA circuit, experimental results demonstrate its efficiency and confirm its accuracy. Results are presented in terms of the mean absolute percentage estimation error being less than 1% for the estimated average power consumption. This work aims at presenting a practical yet efficient power optimization approach that may be extended to online power management.