Impedance Implementation Pattern for PCB Design

The modern communication system, data center and electronics devices deign, are facing increasing challenges in power delivery network design, besides the well-known signal integrity design challenges. In order to make sure the designed product works well to meet design quality, normally platform design guideline will be provided bt Chip suppliers to OEMs or ODMs before OEMs/ODMs product design phase.For Power Delivery Network design, the impedance curve Z(f) from simulation of power rails (like core power, graphic power or memory power…etc.) is required to meet Chip suppliers’ impedance curve Z(f) criteria in each generation of platform. Some customers may not perform Power Integrity (PI) simulation to check if the impedance curve Z(f) of the board power routings can pass Load Line (LL) specification due to resource limitation, no matter in tools or human resource. Instead of relying on actual validation to see if any issue is related to the power rail design.From PI simulation point of view, adding more power shapes/planes or de-coupling capacitors can help to reduce Z(f) value to meet the criteria easily and get better power design quality. If the customers don’t have resource to do PI simulation, they will try to modify the power rail routings in next board re-spin (to add more planes/shapes or de-coupling capacitors) to improved power design quality when the power validation had issue. It will cause additional time and money. If one small symbol pattern can be reserved in board power layout in advanced, it can help to save the PCB re-spin time if the power design hit validation issue.