Control Strategy for Improved After-Etch Overlay at Wafer Edge of DRAM Layers in High-Volume Manufacturing

In high-volume manufacturing (HVM) it is essential to produce wafers with high yield. This requires very tight quality control in the whole process flow. One of the important quality parameters is the so called on-product overlay (OPO), measured either after resist development (ADI) or more importantly after etch process (AEI) of a layer. Further, it is well known that wafer edge often suffers from more severe overlay issue due to process complication there. AEI overlay can be divided into two parts, one with contributors from the Litho step as well as from all other processing steps before the Litho, another is the etching process following the Litho one. For overlay run-to-run control, the former is covered mainly by ADI feedback (FB) loop, while the latter is usually via adding a MTD (metrology to device delta, i.e., delta between AEI and ADI) to the FB loop. A critical DRAM layer which suffers from edge overlay issue is used for this investigation. Simulations show that indeed adding MTD to the FB control can reduce overlay by 16% for whole wafer (for edge zone, 16% as well), while if adding an extra correction per exposure (CPE) generated from AEI, the improvement can be significantly enlarged to a total of 33% (32% for edge). As a comparison, if MTD is skipped in the control loop while keeping the extra CPE, it is still able to achieve 30% reduction for whole wafer (32% for edge).