Study influential factors on lithography imaging in implant layers with wafer topography

Wafer topography becomes more complex in post-gate transistor gate implantation layers from applications exposed by KrF/ArF DUV systems where bottom anti-reflection coatings are undesired. We simulate and analyze the topography impact from wafer stack on lithography imaging using a rigorous method using both planewaves and sector pupils. Response of imaging formation to polarizations, geometries and overlay are particularly addressed. Waveguiding effects with mode excitation are also explained. Understanding these influential factors benefits the imaging performance in terms of resist edge stability and placement error, providing constructive inputs for optimizations.