Cryogenic implantation to boost PFET performance and reduce variability in 3D NAND flows

3D NAND technology requires to have high performance CMOS peri-transistors to drive 3D NAND scaled cells with more stacked layers. The scaled CMOS FET performance needs process technologies to overcome short channel effect (SCE), narrow width effect, and dopant deactivation from further thermal processes after peri-CMOS formation. It is well established that cryogenic implant can be used to boost device performance by reducing implant induced damage or defects in end of range (EOR). Controlling interstitials enable to minimize dopants, such as boron or phosphorus, transient enhanced diffusion (TED) during subsequent thermal process. Therefore, scaled device SCE would be minimized and better device performance with reduced variability can be achieved through uniformly formed implant damage layers. In this paper, we focus on Crion® technology, down to − 100 °C temperature and carbon co-implant to minimize SCE and off leakage performance of PFET in 3D NAND 192L process flow. Device V t variability improvement is also demonstrated. Graphical abstract