A 1400V SiC LDMOS with P-tops and P-buffer for Ultra-low Specific Resistance

A 1400V Silicon carbide (SiC) lateral double diffused MOSFET (LDMOS) featured two P-tops and a P-buffer is proposed in this paper. One P-top is arranged at the end of gate polysilicon to prevent precocious breakdown when N-drift concentration is increased. As a result, a lower LDMOS specific on-resistance (R ds,on ) is obtained by increasing the N-drift concentration without degrading breakdown voltage (BV). The other P-top is placed at drain region to introduce an extra electric field peak in horizonal direction. A P-buffer is adopted between P-drift and substrate to optimize vertical electric field. Hence, the BV is significantly improved thanks to the optimized horizontal and vertical electric field. Compared with conventional SiC LDMOS, the BV and R ds,on of the proposed SiC LDMOS are increased by 46.8% and decrease by 34.6%, respectively.