A Fully Synthesizable Injection Locked PLL with Dual-DCO Frequency Tracking in 55nm CMOS

This paper presents a fully synthesizable injection locked phase-locked loop (PLL), with a dual-DCO frequency tracking. The design has been fabricated in 55-nm CMOS and the layout is realized completely by digital flows. The proposed PLL covers a 0.2-to-1.2-GHz tuning range, achieving an absolute rms jitter (integrated from 100kHz to 100MHz) of 3.2ps at 4.3-mW power consumption, with a corresponding jitter-power figure of merit (FoM) of -224dB and the occupied core area is only 0.0225 mm ² .