Analysis and Optimization of an Analog MOSFET with a Slit Well at Channel Center Towards Higher Output Resistance
ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference (ESSDERC)(2022)
摘要
This paper reports on a novel approach to improve and optimize an output resistance (Rout) which is critical to a long-channel analog MOSFET. The Rout degraded by halo doping can be overcompensated by the slit well inserted along the channel center, reaching the target value of 10Mohm*mu m at the channel length of 0.5 mu m. This improvement is brought by the pinch-off generation at the channel center which makes the drain-side half channel act as a buffer layer for the source-side half channel potential against the drain voltage. The increased fitting parameters can be precisely regressed and optimized by the machine-learning based TCAD scheme, maximizing the overall electrical performance including the Rout.
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关键词
Output resistance (Rout),Long-channel,Analog,Halo,Slit well,Drain-induced threshold voltage shift (DITS),Machine-learning,TCAD
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