A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling

Compute-in-memory (CIM) employing resistive random access memory (RRAM) has been widely investigated as an attractive candidate to accelerate the heavy multiplyand-accumulate (MAC) workloads in deep neural networks (DNNs) inference. Supply voltage (VDD) scaling for compute engines is a popular technique to allow edge devices to toggle between high-performance and low-power modes. While prior CIM works have examined VDD scaling, they have not explored its effects on hardware errors and inference accuracy. In this work, we design and validate an RRAM-based CIM macro with a novel error correction code (ECC), called MACECC, that can be reconfigured to correct errors arising from scaled VDD while preserving the parallelism of CIM. This enables RRAM-CIM to perform iso-accuracy inference across different operation modes. We design specialized hardware to implement the MAC-ECC decoder and insert it into the existing compute pipeline without throughput overhead. Additionally, we conduct measurements to characterize the effect of VDD scaling on errors in CIM. The macro is taped-out in TSMC N40 RRAM process, and for 1x1b MAC operations on DenseNet-40 network it achieves 59.1 TOPS/W and 70.9 GOPS/mm(2) at VDD of 0.7V, and 43.0 TOPS/NV and 112.5 GOPS/mm(2) at VDD of 1.0V. The design maintains <1% accuracy loss on the CIFAR-10 dataset across the tested VDDs.