An Alternate Feedback Mechanism for Tsetlin Machines on Parallel Architectures

2022 International Symposium on the Tsetlin Machine (ISTM)(2022)

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摘要
This work proposes an alternative feedback mechanism for the Tsetlin Machine, a nascent machine learning algorithm that accepts binarized input data and uses propositional logic to identify and accumulate sub-patterns from a given entropy. The proposed method monitors and limits the included literals that contribute to the sub-patterns. This permits the algorithm to converge without requiring the class sum, the primary hurdle of a fully parallelized implementation. Empirical results from a custom RISC-V NoC cluster demonstrate up to a 36X reduction in wall-clock runtime for a 2.5% reduction in accuracy using the MNIST dataset. The proposed method outperforms the original feedback mechanism by 2% when the number of accumulated sub-patterns (clauses) are tightly constrained for the same dataset. This is achieved with a 1.8X reduction in wall-clock runtime.
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关键词
Tsetlin Machine,Parallel Architectures,RISC-V
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