Design of Brent Kung Prefix Form Carry Look Ahead Adder

A binary adder is one of the most important digital circuits in microelectronics because data is stored as bits or binary digits. Due to the increasing demand for computing technology, the adder must operate quickly with minimal circuit area and reduced complexity. Due to its much slower binary addition and propagation delay, ripple-carry adder (RCA) can cause significant bottlenecks in the operation speed. Carry-lookahead adder (CLA) eliminates this delay issue at the expense of a tremendous amount of circuit area. Due to these issues, highly capable adders must be implemented to improve the overall performance of the system with as few drawbacks as possible. In this senior design project, a fast adder known as the Brent-Kung adder (BKA) is designed in the parallel prefix form of CLA to investigate its architecture, speed, and circuit complexity. The designed adder is implemented schematically using the Verilog hardware description language on the Quartus Prime software for the electronic design automation (EDA) tool (HDL). The adder is also simulated on the Altera DE2-115 design kit’s field-programmable gate array (FPGA) board. The results from simulation runs and actual hardware can be evaluated for speed comparisons between different types of adder architectures. The primary objective, which was to analyze the design of BKA, its working mechanism, and the parameters involved, has been attained.