Towards designing a hardware accelerator for 3D convolutional neural networks

•The hardware design of 3D CNNs requires massive compute and memory resources.•A 3-dimensional design space exploration is performed to reduce the complexity of the model.•First, an efficient word-length is found that reduces the feature map and kernel sizes.•Next, input data tiling is performed to efficiently utilized the on-chip memory.•Then, different modes of parallelization are explored to minimize the off-chip accesses.•Finally, an FPGA-based complete hardware accelerator is proposed that can achieve a throughput of 1.29TOPs/s in inference stage.