On the Feasibility of an Inverter-Based CMOS Envelope Detector

This paper explores the feasibility of designing an inverter-based CMOS envelope detector for low-power analog signal processing applications. Transistors are biased in the sub-threshold region to minimize current consumption and maximize the voltage conversion gain. The inverter-based design utilizes a bias voltage generated by a buffered charge-scaling digital-to-analog converter circuit to generate a conversion gain of 6.46 V/V with 3.68 nA of current drawn from a supply voltage of 0.5 V in 180 nm CMOS.