A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad

This paper discusses a small-area implementation of high-speed optical receiver. To integrate multiple channels on a chip, the area is a great concern as well as gain, bandwidth, power, noise, and so on. On-chip inductor and on-chip capacitor are area-consuming components. We employ multi-layer inductor and capacitor-under-pad for area reduction. The proposed circuit was fabricated in a 65-nm CMOS, and the measurement results show 64-dB$\Omega$ gain, 32 Gbps operation and 0.71 pJ/bit energy efficiency in 0.066 mm ² active area.