TAC-RAM: A 65nm 4kb SRAM Computing-in-Memory Design with 57.55 TOPS/W Supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network.
2022 IEEE 4th International Conference on Artificial Intelligence Circuits and Systems (AICAS)（2022）
Key words
Analog computing,Energy-efficient SRAM,Convolutional neural networks (CNNs),Dot-product,Edge-computing,In-memory computation
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined