3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology

Taejoong Song,Hakchul Jung,Giyoung Yang,Hoyoung Tang,Hayoung Kim,Dongwook Seo,Hoonki Kim,Woojin Rim,Sanghoon Baek, Sangyeop Baeck,Jonghoon Jung

2022 IEEE Custom Integrated Circuits Conference (CICC)（2022）

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摘要

3nm Gate-All-Around (GAA) technology is introduced to suggest the future of logic transistor with performance, power, and area (PPA) benefit. However, as with the recent advanced technologies, GAA technology also faces the potential challenges to overcome for the optimum PPA. Therefore, Design-Technology Co-Optimization (DTCO) has become more important than ever to maximize technology-to-design benefits of GAA. In this paper, the motivation of DTCO is presented by showing the successful design examples in advanced technologies. Then, the design techniques of standard cell and SRAM compiler are proposed based on DTCO to maximize the benefit of 3nm GAA technology.

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关键词

DTCO,GAA technology,optimum PPA,Gate-All-Around Design-Technology,logic transistor,standard cell,SRAM compiler,performance power and area benefit,Design-Technology Co-Optimization,size 3.0 nm

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