On-Chip Learning in Spintronics-Based Spiking Neural Network for Handwritten Digit Recognition

Spiking Neural Network (SNN) has been shown to consume very low power for inference tasks, but training of such SNN has remained a challenge. In this paper, we use biologically plausible Spike-Time-Dependent-Plasticity-enabled learning to train the SNN through implementation on analog hardware (on-chip learning). We design and simulate the synapses and neurons in the hardware using a combination of spin-orbit-torque-driven domain wall devices and transistor-based electronic circuits. Through this device-circuit-system co-design, we train the SNN on the MNIST data set of handwritten digits. The architecture that we use here has a lower number of network layers than that used previously for MNIST classification. Also, unlike previous reports, we use a semi-supervised mode of learning here. This adds more flexibility to the SNN hardware in terms of training for different machine learning applications.