Area- and Power-Efficient Reconfigurable Architecture for Multifunction Evaluation

In this paper, we propose an area- and power-efficient reconfigurable architecture for multifunction evaluation based on an optimized piecewise linear (PWL) method. The proposed segmentor automatically divides nonlinear functions into the fewest segments with a predefined maximum absolute error (MAE) and fractional bit width of the slope. In addition, a multiplier was optimized via Booth encoding to reduce the number of rows in the partial product matrix. Compressors were used to shorten the critical path. The results of application-specific integrated circuit (ASIC) implementation reveal that all metrics of the proposed architecture are improved for single functions, without any compromise. Moreover, reconfigurable technology was introduced for implementing multiple functions while reusing computing resources. Compared to a corresponding architecture without reuse, the area and power of this reconfigurable architecture are reduced by 37.48% and 45.60%, respectively, at the same frequency.