Gate Stacked (GS) Junctionless Nanotube MOSFET: Design and Analysis

This paper presents Gate Stacked junctionless nanotube gate all around MOSFET (GS JL NT GAA MOSFET) and its investigation for low power circuit applications. In GS architecture, high-k material as dielectrics was placed over SiO 2 which is deposited around the silicon nanotube (for inner and outer surface of silicon nanotube). GS JL NT GAA MOSFET is also compared with non-stacked junctionless nanotube (JL-NT MOSFET) for performance analysis. GS JL NT GAA MOSFET provides a reduced leakage current (~10 −16 ) and high I ON /I OFF ratio (~10 11 ) as compared to non-stacked device. Side spacer of suitable material needs to be selected for enhancing the performance metrics such as I ON /I OFF ratio, SS, DIBL. Furthermore, the spacer length and diameter of core gate also plays vital role for device design. Therefore, GS JL NT GAA MOSFET has low leakage and high switching speed, which leads it for low power circuit applications.