Low-energy real FFT architectures and their applications to seizure prediction from EEG

While many fast Fourier transform (FFT) architectures have been presented for computing real-valued FFT (RFFT), which of these architectures is best suited for low-throughput applications such as bio- medical signals which are typically sampled between 256 Hz and 1 kHz remains unclear. This paper implements and compares throughput, resources, and energy consumption of three different hardware architectures for real-valued FFT algorithms using Xilinx Ultra96-V2 FPGA development board. The RFFT architectures exploit the conjugate symmetry property of the real signals, thereby eliminating about half of the computations compared to a complex FFT. The three FFT architectures investigated in this paper include: single processing element (SPE), pipelined, and in-place . It is shown that, for a 256-point RFFT, using FPGA, the in-place architectures require the least device resources when compared to the pipelined architectures, while the throughput of the pipelined architectures is approximately 8 times that of the in-place architecture. These RFFT architectures are then used to generate feature vectors for a machine-learning based epileptic seizure prediction system. The seizure prediction system using the various RFFT architectures are then realized in Xilinx Ultra96-V2 FPGA development board and the power consumption values of the overall system using these architectures are compared. It is shown that the pipelined implementation of the feature extraction core results in ≈ 30% reduction in power consumption of the entire system than the in-place implementation for the same target clock frequency, as the pipelined architecture has a higher throughput and hence is idle for majority of the computation time.