An efficient bicubic interpolation implementation for real-time image processing using hybrid computing

Bicubic interpolation is a classic algorithm in the real-time image processing systems, which can achieve good quality at a relatively low hardware cost, and is also the fundamental component of many other much more complex algorithms. However, the multiply-accumulate units (MAC) in the bicubic require massive resources in the hardware-based implementation, which limits the use of the bicubic algorithm. In this article, a hybrid architecture of fix-point and stochastic computing is proposed to reduce the hardware resource consumption by computing the low-weight bits ambiguously. The proposed architecture is tested on standard image sets to survey the performance and is implemented on Intel Cyclone V and Xilinx Virtex-II targets to verify the hardware consumption. The experimental results show that the proposed architecture achieves significant resource reduction and even higher image processing speed compared to the existing architectures with comparable performance.