Embedded FPGA Controllers for Current Compensation Based on Modern Power Theories

This work compares the performance of two embedded FPGA controllers that can be used in Active Parallel Power Filters (APPF). Both controllers are validated through the FPGA-in-the-loop (FIL) technique, the algorithm's synthesis is accomplished using the Quartus II (R) platform, and the board used is from Altera(R)-Cyclone IV DE2-115. The main difference between the controllers resides in the power theories used to obtain the currents for compensation. The results confirm that the FPGA is a suitable digital device for the parallel operation of multiple compensators and calculation stages, being a viable solution for the requirements imposed in the control of APPF. Furthermore, the effectiveness of the FIL technique for validating the operation of digital circuits and control systems is also confirmed. Finally, a comparison between the processing costs of each of the implemented power theories is presented to guide novel proposals.