Scalable FPGA hardware accelerator for SVM inference

In this paper we present a scalable hardware architecture implementing the Support Vector Machine (SVM) binary classification in a Xilinx Zynq FPGA. Our design utilizes a hardware friendly version of the RBF kernel running at 175MHz and taking 11.8 mu s to process 4096 support vectors with 15 features and 12 bit precision. The architecture is pipelined and calculates the L1-norm part of the hardware friendly kernel iteratively. The model is stored in on-chip memory.