A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications

A novel phase frequency detector design is introduced in this study, which removes dead and blind zone issues by eliminating reset path, therefore accelerating the acquisition process. High speed, low power and minimal phase noise are all characteristics of the proposed circuit. The circuit is designed in the Cadence Virtuoso environment and is implemented in CMOS GPDK 180 nm library using a 1.8 V supply voltage. Post-layout simulations have been conducted to ensure that the findings are accurate. The circuit's robustness is tested over process, voltage and temperature fluctuations. The suggested PFD achieves a phase noise of -159.17 dBc/Hz, which is significantly lower than other published circuits. This PFD dissipates 10.25 mu W of power at its maximum operating frequency of 10 GHz. The PFD encompasses an area of 275 mu m(2). The proposed PFD outperforms other PFD circuits in the literature, making it ideal for applications requiring minimal jitter, low power, etc.