A Time Varying Capacitance as Load to Study Area Efficient Arithmetic Circuits

VLSI computing is critical in chip fabrication in today's digital age. Moore's law demands that "the number of transistors on a microchip doubles every two years" in addition to that "the count of transistors employed in a chip size is reduced". As a result, this rule is dictating the electronics industry by reducing chip area, size, and power consumption while simultaneously enhancing chip fabrication strength. The arithmetic circuits are constructed in this work, by boosting the efficiency of circuits by considering die space as a constraint. Overall, arithmetic circuits have a bunch of usages in processing architecture. The XOR gate and multiplexer are utilized in this study to make compressor circuits more efficient by taking into account area, power, and delay. To examine the arithmetic circuit's performance, the load capacitance is customized and the power dissipation across the capacitor is studied.