Buried Power Rail Integration for CMOS Scaling Beyond the 3 Nm Node
A. Gupta,Z. Tao,D. Radisic,H. Mertens,O. Varela Pedreira,S. Demuynck,J. Boemmels,K. Devriendt,N. Heylen,S. Wang,K. Kenis,L. Teugels,F. Sebaai,C. Lorant,N. Jourdan,B. T. Chan,S. Subramanian,F. Schleicher,A. Peter,N. Rassoul, Y. Siew,B. Briggs,D. Zhou,E. Rosseel,E. Capogreco,G. Mannaert,A. Sepulveda,E. Dupuy,K. Vandersmissen,B. Chehab,G. Murdoch,E. Altamirano Sanchez,S. Biesemans,Zs Tokei,E. Dentoni Litta,N. Horiguchi ADVANCED ETCH TECHNOLOGY AND PROCESS INTEGRATION FOR NANOPATTERNING XI（2022）
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