An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine.

Justin M Correll,Lu Jie,Seungheun Song,Seungjong Lee,Junkang Zhu,Wei Tang, Luke Wormald,Jack Erhardt,Nicolas Breil,Roger Quon,Deepak Kamalanathan,Siddarth A Krishnan,Michael Chudzik,Zhengya Zhang,Michael P Flynn,Wei D Lu

Symposium on VLSI Technology (VLSI Technology)（2022）

Cited 14|Views21

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Abstract

Analog compute in memory with Multi-Level Cell (MLC) ReRAM promises highly dense and efficient compute support for machine learning and scientific computing. We present an SoC prototype comprised of four self-contained ReRAM-based CIM tiles and a RISC-V host. The measured raw and normalized peak efficiencies are 20.7 and 662 TOPS/W, respectively. The compute density is 8.4 TOPS/mm ² .

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Key words

multilevel cell ReRAM,machine learning,scientific computing,SoC prototype,ReRAM-based CIM tiles,measured raw peak efficiencies,normalized peak efficiencies,compute density,analog compute in memory,RISC-V host

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