FPGA-based Accelerators System with Low Latency Autonomous DMA Engine

Recently, computing systems have comprised specialized computing components such as FPGAs, GPUs, and various ASIC accelerators to enhance efficiency and performance. We proposed a queue structure mechanism to communicate between CPUs-FPGAs and offload tasks onto FPGAs asynchronously. This paper presents an FPGA system with a low latency autonomous DMA engine to enhance efficiency and performance. We build the system installed in eight FPGAs in which a customized DMA engine is implemented and evaluate communication performance including Software Stack for a single FPGA and the communication latency of an FPGA chain. In a single FPGA, our system achieves DMA read bandwidth of up to 68.5% and DMA write bandwidth of up to 62.2% for PCIe Gen3 x16 theoretical performance. An FPGA chain of up to 8 FPGAs in 4MB data size has latency of 3.7 milliseconds, which under half that when using the existing DMA method(7.6 milliseconds).