Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations

Input/Output transistor are expected to significantly improve power-performance to sustain the expected need of future 3D NAND Flash product for Big Data. In this work we present an HKMG thermally stable platform for next generation NAND I/O periphery devices. We propose a methodology to benchmark power and area device platform trade-off. Key element of the packaged product and different circuit design topologies are considered. We conclude that significant area reduction in the critical driver area combined with power saving can be achieved, providing guidelines for memory designers and system architect of next generation NAND products