High Power Supply Rejection LDO Regulator for Switching Applications

The paper describes design and analysis of a Low-Dropout Regulator (LDO) with a high value of the power supply rejection (PSR) at high frequencies (above 10MHz). The proposed LDO was designed in a standard 65 nm CMOS technology. The output of the designed LDO can be adjusted by the voltage reference used in the LDO. The obtained results prove a very good PSR parameter at frequencies above 10 MHz, where the value of -40 dB is observed in the worst case. Additionally, the designed LDO topology exhibits promising load regulation properties even for a low value of the output capacitor. The proposed LDO can be fully integrated on a chip, and used in complex switching converter Systems on-Chip (SoC), where a high value of PSR is required.