A C-Band Commutated-LC-Negative-R Delay Circuit with Harmonic Power Recycling Achieving 1.5-ns Delay, 1.4-GHz BW, and 6-dB IL

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)(2022)

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摘要
This work presents a commutated-LC-negative-R delay circuit for broadband signal processing at RF. It introduces negative resistance to compensate inductor loss in a commutated­- LC broadband delay circuit, and unveils a new capability of time-varying RF circuits that we call harmonic power recycling. For a time-invariant circuit or an N -path filter circuit, its desired passband consists of only one harmonic. Hence, energies at all other harmonics provided by the broadband negative resistance are wasted. In contrast, a commutated-LC broadband delay circuit has multiple harmonics across its passband, recycling the wasted RF energies from the negative resistance. This harmonic power recycling results in improved noise figure and low dc power in addition to reduced insertion loss (IL). A proof-of-concept CMOS delay line is implemented, achieving 1.5-ns delay, 1.4-GHz instantaneous bandwidth (BW), and 6-dB IL at the C band.
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关键词
Cmos,delay,harmonic,linear periodically time varying,low noise,N-path filter,radio frequency
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