Majority Logic Based In-Memory Comparator

To conquer the von Neumann bottleneck, it is necessary to shift computation to the place where data resides. In this work, we present a methodology to move the comparator circuit to the memory array. A binary comparator is implemented in a transistor-accessed ReRAM (Resistive Random Access Mem-ory) array using majority logic. The majority primitive is a better logic primitive than NAND/NOR/IMPLY primitives for arithmetic intensive operations and also can be realized in memory array efficiently as a READ operation. Using Majority gates and vast gate-level parallelism in the array, comparator is implemented optimally, latency and energy-wise. Using the methodology presented for 1-bit and 8-bit, any n-bit comparator can be realized in 6 + 4log 2 n cycles. Moreover, a general transistor-accessed memory array can be used to implement the proposed comparator without the need for any supreme modifications to the memory peripherals and is efficient as well in terms of energy.