Circuit Design Flow dedicated to 3D vertical nanowire FET
2022 IEEE Latin American Electron Devices Conference (LAEDC)(2022)
Abstract
To continue transistor downscaling beyond lateral 7nm devices, gate-all-around (GAA) junction-less vertical nanowire field effect transistors (VNWFET) represent a promising option. This invited paper presents the circuit design flow based on a vertical junctionless transistor technology. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), DC characterization, compact modelling, EM simulation and parameter extraction are described in details. Using this circuit design flow, a set of innovative 3D circuit architectures are explored.
MoreTranslated text
Key words
Compact modelling,DC characterization,parasitics extraction,EM simulation,VNWFET,3D logic circuit simulation
AI Read Science
Must-Reading Tree
Example
![](https://originalfileserver.aminer.cn/sys/aminer/pubs/mrt_preview.jpeg)
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined