Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization
ISCAS(2022)
摘要
In this paper, two approximate 3x3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2x2 multiplier to produce an 8x8 multiplier with low error-rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset.
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关键词
hardware-driven co-optimization,approximate computing,low error-rate multiplier design,low DNN accuracy loss
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