A 325-μW step-16 digital-sensor based on dual-delay-chain in 180-nm CMOS

The paper presents a step-16 digital-sensor (DS) architecture based on dual-delay-chain (DDC) suitable for embedded applications and security chips. The DDC structure utilizes the sensitivity discrepancy of two sensing units to detect the working condition and it can overcome the clock skew and state rollback issues in traditional DS with lower power consumption. In order to accurately analyze the work principle of DDC, a linear model is proposed to quantitatively estimate the detection range and precision. Furthermore, a DDC dimensioning algorithm is presented to iterately calculate the optimal design of DDC in specific process. Fabricated in 180-nm CMOS, the step-16 DS architecture based on DDC prototype occupies a compact area of 520μm × 60 μm. It can sense the voltage range of 1.4V–2.1 V and the temperature range of −10°C–110 °C, and achieves the temperature precision of 0.075 Step/°C when consuming only 325 μW, corresponding to the work condition (1.8 V, 26 °C).