Study of Analog Weights Based Computing-in-Memory (CIM) using a Highly-Reliable and Small-Noise Vertical-Channel Gate-All-Around Split-Gate Floating Gate NOR Flash for Vector Matrix Multiplication (VMM) Accelerator

We develop a novel vertical-channel gate-all-around (GAA) split-gate floating gate (FG) NOR Flash memory device that has very small RTN noise ( $< 1.5\%$ ), tunable and tight Icell (weight) with extremely small Ioff $\sim \mathrm{p}A$ , excellent retention and read-disturb free reliability in order to enable the analog computing-in-memory (CIM) for high-bandwidth VMM accelerator in various AI applications. To support 4-bit resolutions in edge computing, we can directly provide 4-bit weight of $0\sim 15$ Icell levels (0~3uA) by means of the combinations of 3 cells with 5 levels in each cell, controlled by the bitline switches (BLT). We can produce sigma/mean of 4-bit analog weights in between 4-9% to support sufficient accuracy for deep neural network (DNN). However, we find difficulty in producing analog WL inputs because of the challenges in the transconductance (gm) mismatch (variation) of memory cells. We therefore distribute the 4-bit inputs to plural WL's (select gate (SG) in our design) with single-level bias for accuracy concern. Because of extremely small OFF state current $(\sim \text{pA})$ and moderate ON-state Icell, our vertical GAA FG NOR device can support hundreds of inputs signal in one VMM computing with a steady computing bandwidth (several TOPS at 4bit) for the stationary big data. This novel Flash memory VMM accelerator can complement the Von-Neuman digital computing in saving the large stationary data movements in DRAM I/O. Applications of analog VMM accelerator include DNN inference, cosine similarity search, and digital annealing, etc.