Hybrid III–V/Si-CMOS PDK for Monolithic Heterogeneously-Integrated III–V/Si Technology Platforms

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)(2020)

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摘要
The needs of electronics are endless. The complexity in designing a circuit to meet high demand markets has increased daily. Furthermore, the urge for high power gain for high-efficiency RF applications leads to searching a replacement of Si material. III–V compound semiconductor (CS) materials provide a promising technology booster but integrating into the state-of-the-art Si equipment for VLSI faces some challenges for circuit designs and device fabrication. To ease the design complexity, Process Design Kit (PDK) has been widely used for modern semiconductor designs. This paper presents cross-platform III–V/Si circuit simulation, schematic and layout design, and integration of III–V/Si design verification for VLSI on 200-mm wafer in Si CMOS fabrication environment.
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关键词
monolithic heterogeneously-integrated III-V-silicon technology platforms,VLSI,CMOS fabrication environment,hybrid III-V-silicon-CMOS PDK,layout design,schematic design,semiconductor designs,Process Design Kit,design complexity,circuit designs,III-V compound semiconductor materials,high-efficiency RF applications,size 200 mm,Si
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