Hardware Flexible Systolic Architecture for Convolution Accelerator in Convolutional Neural Networks

A flexible systolic architecture to achieve hardware acceleration in the convolution operation for convolutional neural networks (CNNs) is described in this paper. The main architecture feature is the capability to be adapted to perform the convolution from different main hyperparameters typically required in CNN stages, like input feature map and filter sizes. The proposed architecture is applied in processing the convolution stages for different pretrained CNNs to classify images size of 28x28 pixels from MNIST database with filter sizes of 3x3, 5x5, 7x7, 9x9 and 11x11. The proposed architecture goal is to reduce the processing data time without depending on a single CNN thanks to its adaptability, scalability, data reuse and the use of different data processing parallelisms. The reported architecture was described in VHDL taking as reference a FPGA Cyclone V SE 5CSXFC6D6F31C6N and the results shown were obtained by simulation.